1. Field of the Invention
This invention relates to integrated circuit devices and more particularly to an improved Emitter Coupled Logic (ECL) bipolar memory cell.
2. Background Art
The basic structure of an Emitter Coupled Logic (ECL) bipolar memory cell comprises a pair of memory transistors cross coupled to form a flip-flop circuit. The collectors of the memory transistors are respectively connected to the Vcc word line either through a resistive load or through a PNP load. To connect the cell to bit lines, either a diode design or an additional emitter design is used as respectively shown in FIGS. la and 1b representing prior art ECL structures.
Integrated Injection Logic (I.sup.2 L) or merged transistor logic has also used in memory applications wherein the Vcc word line I is coupled to the memory cell through a PNP load having its collector connected to the base of the memory transistor and the base of the PNP load is connected to word line II. Typical of such a construction is the bipolar memory cell shown in Fulton U.S. Pat. 3,909,807. However, this type of logic has the disadvantage that the cell swings are very small, i.e, about 0.2 volts which creates problems with sensing the state of the cell. This also makes the design more sensitive to noise which can, therefore, make the cell difficult to read. Such designs have also tended to be slow due to the saturated nature of the circuit operation. Some of the problems of I.sup.2 L technology are discussed by Agraz-Guerena et al in "0XIL, A Versatile Bipolar VLSI Technology" in IEEE Journal of Solid-State Circuits, Vol SC-15, No. 4, August, 1980 at pp. 462-466.
On the other hand, ECL designs, as described above, have been quite suitable in the past for cells which are large, i.e., cells used in L.S.I and, in some instances, VLSI structures. The space taken by the device was not critical, thus permitting a number of contact areas and isolation tubs. For example, Dorler et al in "A 1024-Byte ECL Random Access Memory using Complimentary Transistor Switch (CTS) Cell", IBM Journal of Research and Development, Vol. 25, No. 3 (May 1981), pp. 126-134, show, at page 128, shows a modified ECL structure having multiple tubs.
However, as devices using ECL circuitry shrank in size, the number of contacts and the size of isolation areas became the constraint resulting in the need to reduce the number of such contacts and to reduce the size of the isolation areas, and to locate all of the components of a particular cell in the same tub. This, in turn, has resulted in the reduction of storage capacitance which creates a problem of added sensitivity to parasitic charges generated by alpha particles striking the integrated circuit structure (alpha strike) which can results in soft errors. Reduced size also can result in PNPN latch-up due to common tub-bit line contact.